Job Description

Job description:

Job Description

We are seeking a highly detail-oriented "Physical Design IPQA Engineer" to ensure the silicon-readiness and high-quality delivery of our IP portfolio. In this role, you will be responsible for the end-to-end Physical Design verification flow, utilizing CrossCheck and industry-standard EDA tools to validate GDSII, LEF, and Netlist consistency, with a specific focus on "TSMC advanced process nodes".

Key Responsibilities
● IPQA Execution： Perform comprehensive Physical Design checks, including Pin Label validation, GDS/CDL uniqueness, and GDS2RH view verification.
● Advanced Node Validation：Ensure all IP deliverables adhere strictly to "TSMC N3P and N2P" design rules and integration requirements.
● Cross-Tool Validation：Utilize CrossCheck tools to identify inconsistencies between timing models (lib), physical abstracts (LEF), and layout data (GDS).
● Physical Verification：Run and debug sign-off quality DRC (Design Rule Check) and LVS (Layout vs. Schematic) to ensure zero-defect IP delivery.
● EDA Tool Integration：Work within Synopsys (SNPS) and Cadence (CDNS) environments to perform LEF consistency checks and ensure compatibility across multiple PD flows.
● Quality Reporting：Document IPQA violations, coordinate with design teams for fixes, and provide final quality sign-off reports. Required Technical Skills |
● PD IPQA Expertise：Proven experience in IP Quality Assurance with a focus on the physical domain.
● Foundry Knowledge：Deep familiarity with "TSMC advanced nodes", specifically "N3P and N2P" process technologies.
● Design Collaterals：Extensive experience handling and validating "TSMC design collaterals", including PDKs, techfiles, and foundation IP kits.

● Tool Proficiency：Hands-on experience with CrossCheck and standard physical verification tools (e.g., Calibre, IC Validator, or Pegasus).
● Format Knowledge：Deep understanding of IP deliverables including GDSII, LEF, DEF, CDL, and .lib formats.
● EDA Ecosystem：Familiarity with Synopsys and Cadence Physical Design suites.
● Scripting：Ability to use Tcl, Python, or Perl to automate check runs and parse log files.

Preferred Qualifications
● Experience working with external EDA vendors for tool support and flow enhancement.
● Previous experience in a high-volume IP house or foundry environment.

Profile description:

If your are familiar with the following items, you will be a good fit.

1. CAD Flow / EDA Flow / Design Flow
2. STA (Static Timing Analysis) / Timing Violation
3. Python / Scripting / Automation
4. Power Domain / IR drop / UPF